B- 8 M68040 USER’S MANUAL MOTOROLA
B.3.3 Effect of on the ACU
When the assertion of the reset input (RSTI) signal resets the MC68EC040, the E-bits of
the ACRs are cleared, disabling address access control.
B.4 SPECIAL MODES OF OPERATION
This part of the
M68040 User's Manual
does not apply to the MC68EC040. The
MC68EC040 does not sample the IPL2–IPL0, CDIS, JS0 (DLE on the MC68040), or JS1
(MDIS on the MC68040) pins on the rising edge of RSTI.
An external device asserts RSTI to reset the processor. When power is applied to the
system, external circuitry should assert RSTI for a minimum of 10 BCLK cycles after VCC
is within tolerance. Figure B-5 is a functional timing diagram of the power-on reset
operation, illustrating the relationships between VCC, RSTI, and bus signals. The BCLK
and PCLK clock signals are required to be stable by the time VCC reaches the minimum
operating specification. RSTI is internally synchronized for two BCLKS before being used,
and must meet the specified setup and hold times to BCLK (specifications #51 and #52 in
B.7 MC68EC040 Electrical Characteristics) only if recognition by a specific BCLK rising
edge is required.
Figure B-5. MC68EC040 Initial Power-On Reset Timing