MOTOROLA M68040 USER’S MANUAL B- 7
This bit indicates if the transparent block is write protected. If set, write and read-modify-
write accesses are aborted as if the R-bit in a table descriptor were clear. Refer to 3.2.2
Descriptors for a description of table descriptors.
0 = Read and write accesses permitted.
1 = Write accesses not permitted.
B.3.2 Address Comparison
The following description of address comparison assumes that the ACRs are enabled.
Clearing the E-bit in each ACR independently disables access control, causing the
processor to ignore it.
When an ACU receives a physical address, the privilege mode and the eight high-order
bits of the address are compared to the block of addresses defined by the two ACRs for
the corresponding ACU. Each block of address space for an ACR contains an S-field, a
BASE ADDRESS field, and an ADDRESS MASK field. The S-field allows for matching
either user or supervisor accesses (or both). Setting a bit in the ADDRESS MASK field
causes the corresponding bit of the ADDRESS BASE to be ignored in the address
comparison and privilege mode. Setting successively higher order bits in the ADDRESS
MASK field increases the size of the block of address space.
The address for the current bus cycle and an ACR address match when the privilege
mode and address bits for each (not including the masked bits) are equal. Each ACR
specifies write protection for the block of address space. Enabling write protection for a
block of address space causes the abortion of write or read-modify-write accesses to the
block, and an access error exception occurs.
By appropriately configuring an ACR, flexible mappings can be specified. For example, to
control access to the user address space, the S-field equals $0, and the ADDRESS MASK
field equals $FF in all four ACRs. To control access to the supervisor address space
($00000000–$0FFFFFFF) with write protection, the BASE ADDRESS field = $0X, the
ADDRESS MASK field equals $0F, the W-bit is set to one, and the S-field = $1. The
inclusion of independent ACRs in both the instruction ACU (IACU) and data ACU (DACU
provides an exception to the merged instruction and data address space, allowing
different access control for instruction and operand accesses. Also, since the instruction
memory unit is only used for instruction prefetches, different instruction and data ACRs
can cause PC relative operand fetches to be translated differently from instruction
Matching either of the ACRs in a corresponding ACU during an access to a memory unit
completes the access with the ACU. If both registers match, the access uses the xACR0
status bits. Addresses are passed through without translation if there is no match in the
ACRs and no table search occurs. The MC68EC040 does not perform table searches.