B- 6 M68040 USER’S MANUAL MOTOROLA
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LOGICAL ADDRESS BASE LOGICAL ADDRESS MASK E S 0 0 0 U1 U0 0 CM 0 0 W 0 0
Figure B-4. MC68EC040 Access Control Register Format
This 8-bit field is compared with physical address bits A31–A24. Addresses that match
in this comparison (and are otherwise eligible) are accessible.
This 8-bit field contains a mask for the ADDRESS BASE field. Setting a bit in the
ADDRESS MASK field causes the processor to ignore the corresponding bit in the
ADDRESS BASE field. Setting some of the ADDRESS MASK bits to ones obtains
blocks of memory larger than 16 Mbytes. The low-order bits of this field are normally set
to define contiguous blocks larger than 16 Mbytes, although contiguous blocks are not
This bit enables and disables transparent translation of the block defined by this
register. Refer to Section 3 Memory Management Unit (Except MC68EC040 and
MC68EC040V) for details on transparent translation.
0 = Access control disabled.
1 = Access control enabled.
This field specifies the way FC2 is used in matching an address:
00 = Match only if FC2 = 0 (user mode access).
01 = Match only if FC2 = 1 (supervisor mode access).
10, 11 = Ignore FC2 when matching.
U1, U0—User Page Attributes
These two bits drive on the user page attribute signals (UPA1 and UPA0). If an external
bus transfer results from the access, U0 and U1 are echoed to the UPA0 and UPA1
signals, respectively. The user can program these bits to support extended addressing,
bus snooping, or other applications. The MC68EC040 does not interpret these bits.
CM —Cache Mode
This field selects the cache mode and access serialization for a page as follows:
00 = Cachable, Write-through
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
Detailed information on caching modes is available in Section 4 Instruction and Data
Caches, and information on serialization is available in Section 7 Bus Operation.