The DLE and MDIS pin names have been changed to JS0 and JS1, respectively.
The MC68EC040 does not implement the DLE mode, multiplexed, or output buffer
impedance selection modes of operation. The MC68EC040 implements only the
small output buffer mode of operation. All timing and drive capabilities of the
MC68EC040 are equivalent to those of the MC68040 in the small buffer mode of
The MC68040 MDIS and DLE pin names have been changed to JS1 and JS0
respectively. During normal operation, the JS1 and JS0 pin cannot float, they must be tied
to GND or Vcc directly or through a resistor. During board testing, these pins retain the
functionality of the JTAG scan of the MC68040 for compatibility purposes. Refer to
Section 6 IEEE 1149.1 Test Access Port (JTAG) for details concerning IEEE
Standard Test Access Port and Boundary Scan Architecture
The information in this section replaces the information in Section 3 Memory
Management Unit (Except MC68EC040 and MC68EC040V). When reading Section 4
Instruction and Data Caches, disregard any references to the MMU; remember the
functionality of the access control registers has replaced that of transparent translation
registers. The MC68EC040 contains two independent ACUs, one for instructions and one
for data. Each ACU allows memory selections to be made requiring attributes particular to
peripherals, shared memory, or other special memory requirements. The following
paragraphs describe the ACUs and the access control registers contained in them.
B.3.1 Access Control Registers
Each ACU has two independent access control registers (ACRs). The instruction ACU
contains the instruction access control registers (IACR0 and IACR1). The data ACU
contains the data access control registers (DACR0 and DACR1). Both ACRs provide and
control status information for access control of memory in the MC68EC040. Only
programs that execute in the supervisor mode using the MOVEC instruction can directly
access the ACRs.
The 32-bit ACRs each define blocks of address space for access control. These blocks of
address space can overlap or be separate, and are a minimum of 16 Mbytes. Three
blocks are used with two user-defined attributes, cachability control and optional write
protection. The ACRs specify a block of address space as serialized noncachable for
peripheral selections and as write-through for shared blocks of address space in multi-
processing applications. The ACRs can be configured to support many embedded control
applications while maintaining cache integrity. Refer to Section 4 Instruction and Data
Caches for details concerning cachability. Figure B-4 illustrates the ACR format.
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