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MOTOROLA M68040 USER’S MANUAL A- 11
A.6.6 Output AC Timing Specifications (see Figures A-5* to A-9)
20 MHz 25 MHz 33 MHz
Num Characteristic Min Max Min Max Min Max Unit
11 BCLK to Address, CIOUT, LOCK, LOCKE ,
PSTx, R/W, SIZx, TLNx ,TMx, TTx, UPAx
Valid
11.5 35 9 30 6.5 25 ns
12 BCLK to Output Invalid (Output Hold) 11.5 9 — 6.5 ns
13 BCLK to TS Valid 11.5 35 9 30 6.5 25 ns
14 BCLK to TIP Valid 11.5 35 9 30 6.5 25 ns
18 BCLK to Data-Out Valid 11.5 37 9 32 6.5 27 ns
19 BCLK to Data-Out Invalid (Output Hold) 11.5 9 — 6.5 ns
20 BCLK to Output Low Impedance 11.5 9 — 6.5 ns
21 BCLK to Data-Out High Impedance 11.5 25 9 20 6.5 17 ns
38 BCLK to Address, CIOUT, LOCK, LOCKE ,
R/ W, SIZx, TS, TLNx, TMx, TTx, UPAx High
Impedance
11.5 23 9 18 6.5 15 ns
39 BCLK to BB, TA, TIP High Impedance 23 33 19 28 14 25 ns
40 BCLK to BR , BB Valid 11.5 35 9 30 6.5 23 ns
43 BCLK to MI Valid 11.5 35 9 30 6.5 25 ns
48 BCLK to TA Valid 11.5 35 9 30 6.5 25 ns
50 BCLK to IPEND, PSTx, RSTO Valid 11.5 35 9 30 6.5 25 ns
* Output timing is specified for a valid signal measured at the pin. Timing is specified driving an unterminated 30-
transmission line with a length characterized by a 2.5-ns one-way propagation delay. Buffer output impedance is
typically 30 ; the buffer specifications include approximately 5 ns for the signal to propagate the length of the
transmission line and back.
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