Table 1-4. Instruction Set Summary (Continued)
Opcode Operation Syntax
BTST –(bit number of Destination) ø Z; BTST Dn,<ea>
BTST #<data>,<ea>
CAS CAS Destination – Compare Operand ø cc;
if Z, Update Operand ø Destination
else Destination ø Compare Operand
CAS Dc,Du,<ea>
CAS2 CAS2 Destination 1 – Compare 1 ø cc;
if Z, Destination 2 – Compare ø cc;
if Z, Update 1 ø Destination 1;
Update 2 ø Destination 2
else Destination 1 ø Compare 1;
Destination 2 ø Compare 2
CAS2 Dc1–Dc2,Du1–Du2,(Rn1)–(Rn2)
CHK If Dn < 0 or Dn > Source
then TRAP
CHK <ea>,Dn
CHK2 If Rn < LB or If Rn > UB
then TRAP
CHK2 <ea>,Rn
CINV If supervisor state
then invalidate selected cache lines
else TRAP
CINVL <caches>, (An)
CINVP <caches>, (An)
CINVA <caches>
CLR 0 ø Destination CLR <ea>
CMP Destination – Source ø cc CMP <ea>,Dn
CMPA Destination – Source CMPA <ea>,An
CMPI Destination – Immediate Data CMPI #<data>,<ea>
CMPM Destination – Source ø cc CMPM (Ay)+,(Ax)+
CMP2 Compare Rn < LB or Rn > UB
and Set Condition Codes
CMP2 <ea>,Rn
CPUSH If supervisor state
then if data cache push selected dirty data
cache lines; invalidate selected cache lines
else TRAP
CPUSHL <caches>, (An)
CPUSHP <caches>, (An)
CPUSHA <caches>
DBcc If condition false
then (Dn–1 ø Dn;
If Dn –1
then PC + dn ø PC)
DBcc Dn,<label>
DIVS, DIVSL Destination ÷ Source ø Destination DIVS.W <ea>,Dn 32 ÷ 16 ø 16r:16q
DIVS.L <ea>,Dq 32 ÷ 32 ø 32q
DIVS.L <ea>,Dr:Dq 64 ÷ 32 ø 32r:32q
DIVSL.L <ea>,Dr:Dq 32 ÷ 32 ø 32r:32q
DIVU, DIVUL Destination ÷ Source ø Destination DIVU.W <ea>,Dn 32 ÷ 16 ø 16r:16q
DIVU.L <ea>,Dq 32 ÷ 32 ø 32q
DIVU.L <ea>,Dr:Dq 64 ÷ 32 ø 32r:32q
DIVUL.L <ea>,Dr:Dq 32 ÷ 32 ø 32r:32q
EOR Source Destination ø Destination EOR Dn,<ea>
EORI Immediate Data Destination ø Destination EORI #<data>,<ea>
EORI to CCR Source CCR ø CCR EORI #<data>,CCR
EORI to SR If supervisor state
then Source SR ø SR
else TRAP
EORI #<data>,SR
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com