A.5.1 Unimplemented Floating-Point Instructions and Exceptions
All legal MC68040 and MC68881/MC68882 floating-point instructions are defined as
unimplemented floating-point instructions on the MC68LC040. These instructions
generate a format $4 stack frame during exception processing before taking an F-line
exception. These instructions trap as an F-line exception, and the F-line exception handler
can emulate them in software to maintain user-object-code compatibility.
The MC68LC040 assists the emulation process by distinguishing unimplemented floating-
point instructions from other unimplemented F-line instructions. To aid emulation, the
effective address is calculated and saved in the format $4 stack frame. This simplifies and
speeds up the emulation process by eliminating the need for the emulation routine to
determine the effective address and by providing information required to emulate the
instruction on the exception stack frame in the supervisor address space. However, the
floating-point instruction can reside in user space; therefore, the floating-point
unimplemented exception handler may need to access user instruction space. The
following processing steps occur for an unimplemented floating-point instruction:
1. When an unimplemented floating-point instruction is encountered, the instruction is
partially decoded, and the effective address is calculated, if required.
2. The processor waits for all previous integer instructions, write-backs, and associated
exception processing to complete before beginning exception processing for the
unimplemented floating-point instruction. Any access error that occurs in completing
the write-backs causes an access error exception, and the resulting stack frame
indicates a pending unimplemented floating-point instruction exception. The access
error exception handler then completes the write-backs in software, and exception
processing for the unimplemented floating-point instruction exception begins
immediately after return from the access error handler.
3. The processor begins exception processing for the unimplemented floating-point
instruction by making an internal copy of the current SR. The processor then enters
the supervisor mode and clears the trace bits (T1 and T0). It creates a format $4
stack frame and saves the internal copy of the SR, PC, vector offset, calculated
effective address, and PC value of the faulted instruction in the stack frame.
The effective address field of the format $4 stack frame contains the calculated
effective address of the operand for the faulted floating-point instruction using the
addressing mode in which the effective address is calculated. For immediate and
register direct addressing modes, this field is $0. The saved PC value is the logical
address of the instruction that follows the unimplemented floating-point instruction.
This value will be restored during RTE execution. The vector offset format number
($4) is used for this eight-word stack frame. Note that an MC68040 cannot correctly
handle a stack format $4. The PC of the faulted instruction contains a long-word PC
of the floating-point instruction that caused the trap to occur. The information is
provided so that the instruction is available for software emulation of floating-point
instructions. The processor generates exception vector number 11 for the
unimplemented F-line instruction exception vector, fetches the address of the F-line
exception handler from the exception vector table, and begins execution of the
handler after prefetching instructions to fill the pipeline. Refer to Section 8
Exception Processing for details about exception processing.
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