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MOTOROLA M68040 USER’S MANUAL A- 1
APPENDIX A
MC68LC040
NOTE
All references to MC68LC040 also apply to the MC68040V.
Refer to Appendix C MC68040V and MC68EC040V for more
information on the MC68040V.
The MC68LC040 is Motorola’s integer-only version of the MC68040 third-generation,
M68000-compatible, high-performance, 32-bit microprocessor. The MC68LC040 is a
virtual memory microprocessor with a highly integrated architecture that provides very
high performance in a monolithic HCMOS device. On a single chip, the MC68LC040
integrates an MC68040-compatible integer unit and fully independent instruction and data
demand-paged memory management units (MMUs), including independent 4-Kbyte
instruction and data caches. A high degree of instruction execution parallelism is achieved
through the use of a six-stage instruction pipeline, multiple internal buses, and a full
internal Harvard architecture, including separate physical caches for both instruction and
data accesses. The MC68LC040 also directly supports cache coherency in multimaster
applications with dedicated on-chip bus snooping logic.
The MC68LC040 achieves its high performance through the use of the MC68040 integer
unit. The six-stage pipeline operates on up to six instructions concurrent with MMU,
cache, and bus controller operations. Multiple internal buses, separate data and
instruction caches, and a sophisticated bus controller allow internal units to operate
concurrently and decouple the MC68LC040 from the external bus. The internal caches
and the decoupling of the external bus allow for an external memory subsystem to be built
from slower and less expensive memories with minimal impact to the overall system
performance. The potential for a low-cost system design with the price/performance of the
MC68LC040 makes it a good choice for embedded microprocessor applications as well as
central processor applications.
The MC68LC040 is user-object-code compatible with previous members of the M68000
family and is specifically optimized to reduce the execution time of compiler-generated
code. The high level of performance is ideal for integer-intensive applications. The
MC68LC040 is implemented in Motorola’s latest HCMOS technology, providing an ideal
balance between speed, power, and physical device size. Independent data and
instruction MMUs control the main caches and the address translation caches (ATCs).
The ATCs speed up logical-to-physical address translations by storing recently used
translations. The bus snooper circuit ensures cache coherency in multimaster and
multiprocessing applications. The MC68LC040 is pin compatible with the MC68040 and
the MC68EC040. Figure A-1 illustrates a simplified block diagram of the MC68LC040.
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