MOTOROLA M68040 USER’S MANUAL 1- 11
1.9 NOTATIONAL CONVENTIONS
Table 1-3 lists the notation conventions used throughout this manual unless otherwise
Table 1-3. Notational Conventions
Single- And Double-Operand Operations
+ Arithmetic addition or postincrement indicator.
– Arithmetic subtraction or predecrement indicator.
÷Arithmetic division or conjunction symbol.
~ Invert; operand is logically complemented.
⊕Logical exclusive OR
øSource operand is moved to destination operand.
ł ø Two operands are exchanged.
<op> Any double-operand operation.
<operand>tested Operand is compared to zero and the condition codes are set appropriately.
sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion.
TRAP Equivalent to Format ÷ Offset Word ø (SSP); SSP – 2 ø SSP; PC ø (SSP); SSP – 4 ø SSP; SR
ø (SSP); SSP – 2 ø SSP; (Vector) ø PC
STOP Enter the stopped state, waiting for interrupts.
<operand>10 The operand is BCD; operations are performed in decimal.
Test the condition. If true, the operations after “then” are performed. If the condition is false
and the optional “else” clause is present, the operations after “else” are performed. If the
condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc
instruction description as an example.
An Any Address Register n (example: A3 is address register 3)
Ax, Ay Source and destination address registers, respectively.
BR Base Register—An, PC, or suppressed.
Dc Data register D7–D0, used during compare.
Dh, Dl Data registers high- or low-order 32 bits of product.
Dn Any Data Register n (example: D5 is data register 5)
Dr, Dq Data register’s remainder or quotient of divide.
Du Data register D7–D0, used during update.
Dx, Dy Source and destination data registers, respectively.
MRn Any Memory Register n.
Rn Any Address or Data Register
Rx, Ry Any source and destination registers, respectively.
Xn Index Register—An, Dn, or suppressed.