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MOTOROLA M68040 USER’S MANUAL 10-15
10.6 INTEGER UNIT INSTRUCTION TIMINGS (Continued)
BCHG, BCLR, BSETaBFCHG, BFCLR, BFSETb,c BFEXTS, BFEXTUb,d
Addressing
Mode
<ea>
Calculate Execute <ea>
Calculate Execute <ea>
Calculate Execute
Dn 1 3/4 3/4 e6/7 e1/2 e4/5 e
An ——————
(An) 1 3/4 9 2L + 8 9 2L + 7
(An)+ 1 3/4 ————
–(An) 1 3/4 ————
(d 16,An) 2/1 1L + 3/4 9 2L + 8 9 2L + 7
(d 16,PC) ————103
L
+ 7
(xxx).W, (xxx).L 2/1 1L + 3/4 9 2L + 8 9 2L + 7
#<xxx> ——————
(d 8,An,Xn) 3 5/6 10 11 10 10
(d 8,PC,Xn) ————111
L
+ 10
(BR,Xn) 7 1L + 8/1L + 9 13 1L + 13 13 1L + 12
(bd,BR,Xn) 8 1L + 9/1L + 10 14 1L + 14 14 1L + 13
([bd,BR,Xn]) 10 1L + 11/1L + 12 16 1L + 16 16 1L + 15
([bd,BR,Xn],od) 11 1L + 12/1L + 13 17 1L + 17 17 1L + 16
([bd,BR],Xn) 11 3L + 10/3L + 11 17 3L + 15 17 3L + 14
([bd,BR],Xn,od) 12 3L + 11/3L + 12 18 3L + 16 18 3L + 15
NOTES:
a. Bit instruction <ea> calculate and execute times T1/T2 apply to #<xxx>/Dn bit numbers.
b. This instruction interlocks the <ea> calculate and execute stages.
c. If the bit field spans a long-word boundary, add ten and nine clocks to the <ea> calculate and execute times,
respectively. Two memory addresses are accessed in this case.
d. If the bit field spans a long-word boundary, add two clocks to the execute time. Two memory addresses are
accessed in this case.
e. Immediate count specified for both width and offset and width and/or offset specified in register, respectively.
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