MOTOROLA M68040 USER’S MANUAL 10-5
10.2 INSTRUCTION TIMING EXAMPLES
The following examples utilize the instruction timing information given in this section.
Figure 10-1 illustrates the integer unit pipeline flow for the simple code sequence listed.
The three instructions in the code sequence require only a single clock in each pipeline
stage. The TRAPF instructions are also single-clock instructions that function as
C1 C2 C3 C4 C5 C6 C7
P1 A B C N1 N2
P1 A B C N1 N2
P1 A B C N1
Figure 10-1. Simple Instruction Timing Example
C1 The previous instruction (P1) finishes in the <ea> calculate.
C2 MOVE.L (A) starts in the <ea> calculate and requests an immediate extension
word for its effective address.
C3 MOVE.L (A) starts in the <ea> fetch, which fetches the operand at $1000. ADDQ.L
(B) starts in the <ea> calculate stage with the operand encoded in the instruction.
C4 MOVE.L (A) executes in the execute stage, storing the fetched operand in register
D0. ADDQ.L (B) starts in the <ea> fetch with no operation performed. MOVE.L (C)
starts in the <ea> calculate requesting an immediate extension word for its effective
C5 ADDQ.L (B) executes in the execution stage, incrementing D0 by 1. MOVE.L (C)
passes through the <ea> fetch with no operation performed. The next instruction
starts in the <ea> calculate stage.
C6 MOVE.L (C) executes in the execution stage generating a write of D0 to the
C7 The write to memory by MOVE.L (C) occurs to the data memory unit if it is not
busy. If the second TRAPF instruction (N2) in the <ea> fetch stage requires an
operand fetch, the write-back for MOVE.L (C) stalls in the write-back stage since it
is a lower priority.