example, if an execution time is listed as 2L + 1, the lead time is two clocks and the base
time is one for a total execution time of three. The instruction can stall for two clocks
without delaying the instruction execution time.
The <ea> calculate and execute stages operate in an interlocked manner for all
instructions using the brief and full extension word formats. If an instruction using one of
these formats is stalled for more than NL clocks waiting to begin execution in the execute
stage, a similar increase in the <ea> calculate time will result. For example, if the
execution time listed is 2L + 1 and the instruction stalls for three clocks, then the <ea>
calculate time increases by one clock (3 – 1 = 2L). Write-back times are not listed because
they are system dependent and do not affect either <ea> calculate or execute stages of
the pipeline.
Not all addressing modes listed in the following tables for an instruction are valid for all
variations of the instruction. For example, the table for the integer ADD instruction lists
times for both ADD <ea>,Dn and ADD Dn,<ea>. All addressing modes listed are valid for
ADD <ea>,Dn. For ADD Dn,<ea> the following invalid modes should be ignored: An,
(d 16,PC), #<xxx>, (d8,PC,Xn), and modes with BR = PC. Refer to the M68000PM/AD,
M68000 Family Programmer's Reference Manual
for a complete summary of valid
instruction and addressing mode combinations. The instruction timings are based on the
following suppositions unless otherwise noted:
1. All timings are related to BCLK cycles and are for BR = An or suppressed. For BR =
PC, 1 and 1L clocks to the <ea> calculate and execution times unless otherwise
noted. For memory indirect postindexed with suppressed index — ([bd,BR],Xn) or
([bd,BR],Xn,od) with Xn suppressed — times are the same as for memory indirect
preindexed with suppressed index — ([bd,BR,Xn]) or ([bd,BR,Xn],od) with Xn
2. All memory accesses hit in the caches; no table searches occur as a result of ATC
misses except for the operand accesses for the CAS, CAS2, and TAS instructions.
These accesses are implicitly noncachable and force external bus accesses. It is
assumed that external memory has a zero-wait state in this case and that the bus is
granted to the M68040.
The result increases access time equal to the number of clocks for the memory
access (first bus cycle if the operand access results in a line memory access) if
aligned accesses miss in the data cache. As an approximation, this time should be
added to the execution time for each operand fetch generated by the instruction.
3. All accesses are aligned to a byte boundary that is a multiple of the operand size.
For instance, the timing for all long-word accesses assumes that the operands are
on long-word boundaries.
4. The integer execution times for floating-point instructions assume that the floating-
point unit (FPU) is idle.
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