Refer to Section 2 Integer Unit for information on the integer unit pipeline. The <ea>
fetch timing is not listed in the following tables because most instructions require one clock
in the <ea> fetch stage for each memory access to obtain an operand. An instruction
requires one clock to pass through the <ea> fetch stage even if no operand is fetched.
Table 10-2 summarizes the number of memory fetches required to access an operand
using each addressing mode for long-word aligned accesses. The user must perform his
own calculations for <ea> fetch timing for misaligned accesses.
Table 10-2. Number of Memory Accesses
Addressing Mode
Evaluate <ea>
And Fetch
Evaluate <ea>
And Send To
Execution Stage
Dn 0 0
An 0 0
(An) 1 0
(An)+ 1 0
–(An) 1 0
(d 16,An) 1 0
(d 16,PC) 1 0
(xxx).W, (xxx).L 1 0
#<xxx> 0 0
(d 8,An,Xn) 1 0
(d 8,PC,Xn) 1 0
(BR,Xn) 1 0
(bd,BR,Xn) 1 0
([bd,BR,Xn]) 2 1
([bd,BR,Xn],od) 2 1
([bd,BR],Xn) 2 1
([bd,BR],Xn,od) 2 1
In the instruction timing tables, the <ea> calculate column lists the number of clocks
required for the instruction to execute in the <ea> calculate stage of the integer unit
pipeline. Dual effective address instructions such as ABCD –(Ay),–(Ax) require two
calculations in the <ea> calculate stage and two memory fetches. Due to pipelining, the
fetch of the first operand occurs in the same clock as the <ea> calculation for the second
The execute column lists the number of clocks required for the instruction to execute in
the execute stage of the integer unit pipeline. This number is presented as a lead time and
a base time. The lead time is the number of clocks the instruction can stall when entering
the execution stage without delaying the instruction execution. If the previous instruction is
still executing in the execution stage when the current instruction is ready to move from
the <ea> fetch stage, the current instruction stalls until the previous one completes. For
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