uses. The IU identifies a logical address by accessing either the supervisor or user
address space, maintaining the differentiation between supervisor and user modes. The
MMUs use the indicated privilege mode to control and translate memory accesses,
protecting supervisor code, data, and resources from user program accesses. Refer to
Appendix B MC68EC040 for details concerning the MC68EC040 address translation.
Programs access registers based on the indicated mode. User programs can only access
registers specific to the user mode; whereas, system software executing in the supervisor
mode can access all registers, using the control registers to perform supervisory functions.
User programs are thus restricted from accessing privileged information, and the
operating system performs management and service tasks for the user programs by
coordinating their activities. This difference allows the supervisor mode to protect system
resources from uncontrolled accesses.
Most instructions execute in either mode, but some instructions that have important
system effects are privileged and can only execute in the supervisor mode. For instance,
user programs cannot execute the STOP or RESET instructions. To prevent a user
program from entering the supervisor mode, except in a controlled manner, instructions
that can alter the S-bit in the SR are privileged. The TRAP instructions provide controlled
access to operating system services for user programs.
If the S-bit in the SR is set, the processor executes instructions in the supervisor mode.
Because the processor performs all exception processing in the supervisor mode, all bus
cycles generated during exception processing are supervisor references, and all stack
accesses use the active supervisor stack pointer. If the S-bit of the SR is clear, the
processor executes instructions in the user mode. The bus cycles for an instruction
executed in the user mode are user references. The values on the transfer modifier pins
indicate either supervisor or user accesses.
The processor utilizes the user mode and the user programming model when it is in
normal processing. During exception processing, the processor changes from user to
supervisor mode. Exception processing saves the current value of the SR on the active
supervisor stack and then sets the S-bit, forcing the processor into the supervisor mode.
To return to the user mode, a system routine must execute one of the following
instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE, which execute in
the supervisor mode, modifying the S-bit of the SR. After these instructions execute, the
instruction pipeline is flushed and is refilled from the appropriate address space.
The MC68040 integrates the functions of the IU, FPU, and MMU. The registers depicted
in the programming model (see Figure 1-2) provide operand storage and control for these
three units. The registers are partitioned into two levels of privilege modes: user and
supervisor. The user programming model is the same as the user programming model of
the MC68030, which consists of 16, general-purpose, 32-bit registers and two control
registers. The MC68040 user programming model also incorporates the
MC68881/MC68882 programming model consisting of eight, 80-bit, floating-point data
registers, a floating-point control register, a floating-point status register, and a floating-
point instruction address register.
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