Table 9-15, and the user INEX exception handler can choose to modify these values. The
E3 and E1 of the floating-point state frame bits need to be examined to determine which
fields in the floating-point state frame are valid. E3 always takes precedence and must
always be serviced first. Table 9-16 lists the floating-point state frame fields for INEX
exceptions with E3 set or with E3 clear and E1 set. It is possible for an FADD, FSUB,
FMUL, and FDIV to report a post-instruction exception, although these instructions
normally generate a pre-instruction exception. The following example shows why a post-
instruction exception is generated.
FADD FP2,FP0 ; this instruction generates an inexact exception
FMOVE FP0, <ea> ; this instruction is executing when inexact occurs
For this example, assume that the FMOVE instruction starts once the FADD instruction
generates an underflow. Given the register dependency on FP0, the destination of the
FADD instruction, FP0 needs to be resolved prior to the FMOVE instruction execution. For
this example, there is no choice but to have the FADD instruction report a post-instruction
exception immediately. Note that for this case, even though the T-bit of the floating-point
state frame is set (post instruction exception), it does not imply an FMOVE OUT
instruction. Therefore, the effective address field in the format $3 stack frame is invalid.
The FMOVE OUT instruction generates a post-instruction exception. For this case, the
effective address field in the format $3 stack frame points to the destination memory
location. If the destination is an integer data register, the FPIAR points to the F-line word
of the offending instruction, and the F-line word contains the integer data register number.
If the MC68040FPSP unimplemented instruction exception handler is used, there can be
some other cases in which an inexact exception is reported.
The user INEX exception handler examines the E3 bit of the floating-point state frame to
exit from this exception handler. If the E3 bit is set, it must be cleared prior to restoring the
floating-point frame via the FRESTORE instruction. If the E3 bit is clear and the E1 bit is
set, the floating-point frame is discarded. The RTE instruction must be executed to return
to normal instruction flow.
The IEEE 754 standard specifies that inexactness should be
signaled on overflow as well as for rounding. The processor
implements this via the INEX bit in the FPSR AEXC byte.
However, the standard also indicates that the inexact
exception should be taken if an overflow occurs with the OVFL
bit disabled and the INEX bit enabled in the FPSR AEXC byte.
Therefore, the processor takes the inexact exception if this
combination of conditions occurs, even though the INEX1 or
INEX2 bit may not be set in the FPSR EXC byte. In this case,
the INEX bit is set in the FPSR AEXC byte, and the OVFL bit is
set in both the FPSR EXC and AEXC bytes.
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