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MOTOROLA M68040 USER’S MANUAL 9- 37
inexact error to occur that is signaled as INEX1 exception. Furthermore, the subsequent
divide could also produce an inexact result and cause INEX2 to be set in the FPCR EXC
byte. Note that only one inexact exception vector number is generated by the processor. If
either of the two inexact exceptions is enabled, the processor fetches the inexact
exception vector, and the user INEX exception handler is initiated. INEX refers to both
exceptions in the following paragraphs.
The INEX2 exception is the condition that exists when any operation, except the input of a
packed decimal number, creates a floating-point intermediate result whose infinitely
precise mantissa has too many significant bits to be represented exactly in the selected
rounding precision or in the destination data format. If this condition occurs, the INEX2 bit
is set in the FPSR EXC byte, and the infinitely precise result is rounded. Table 9-15 lists
these rounding mode values.
Table 9-15. Divide by Zero Rounding Mode Values
Rounding
Mode Result
RN The representable value nearest to the infinitely precise intermediate value is
the result. If the two nearest representable values are equally near (a tie), then
the one with the least significant bit equal to zero (even) is the result. This is
sometimes referred to as “round nearest, even.”
RZ The result is the value closest to and no greater in magnitude than the infinitely
precise intermediate result. This is sometimes referred to as the “chip mode,”
since the effect is to clear the bits to the right of the rounding point.
RM The result is the value closest to and no greater than the infinitely precise
intermediate result (possibly minus infinity).
RP The result is the value closest to and no less than the infinitely precise
intermediate result (possibly plus infinity).
The INEX1 and INEX2 exceptions are always maskable. Therefore, any INEX exception
goes directly to the user INEX exception handler. The M68040FPSP does not provide any
special handling for the INEX exception. When an INEX2 or INEX1 bit in the FPSR EXC
byte is set, the processor stores the rounded result (listed in Table 9-15), to the
destination. The FPCR MODE byte determines the rounding mode, and the PREC byte
determines the rounding precision if the destination is a floating-point data register.
Otherwise, if the destination is memory or an integer data register, the destination format
determines the rounding precision. If one of the instructions has a forced precision, the
instruction determines the rounding precision. If the INEX2 or INEX1 condition exists and
if the corresponding INEX bit in the FPCR ENABLE byte is set, then the user INEX
exception handler is taken.
a. If the user INEX exception handler is disabled, result is rounded and normal
processing continues.
b. If the user INEX exception handler is enabled, the exception is taken. The INEX
entry in the processor’s vector table points to the user INEX exception handler.
The user INEX exception handler must execute an FSAVE as its first floating-point
instruction. At this point, the destination contains the rounding mode values as listed in
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