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MOTOROLA M68040 USER’S MANUAL 9- 29
exception handler can report. When an operand error occurs, the OPERR bit is set in the
FPSR EXC byte.
Table 9-11. Possible Operand Errors Exceptions
Instruction Condition Causing Operand Error
Native to MC68040
FADD (+inf) + (–inf) or (–inf) + (+inf)
FDIV 0 ÷ 0 or inf ÷ inf
FMOVE to B,W,or L Integer overflow where the source is nonsignaling NAN or +infinity.
FMUL One operand is 0 and other is +inf.
FSQRT Source < 0 or ±inf.
FSUB (+inf) – (+inf) or (–inf) – (–inf)
Nonnative to MC68040
FACOS Source is ±inf, > +1, or < –1
FASIN Source is ±inf, > +1, or < –1
FATANH Source is > +1 or < –1
FCOS Source is ±inf
FGETEXP Source is ±inf
FGETMAN Source is ±inf
FLOG10 Source is < 0
FLOG2 Source is < 0
FLOGN Source is < 0
FLOGNP1 Source is 1
FMOD Floating-point data register is ±inf or source is 0, other operand is not a NAN
FMOVE to P Source exponent > 999 (decimal) or k-Factor > 17
FREM Floating-point data register is ±inf or source is 0, other operand is not a NAN
FSCALE Source is ±inf
FSGLDIV 0 ÷ 0 or inf ÷ inf
FSGLMUL One operand is 0, other operand is inf
FSIN Source is ±inf
FSINCOS Source is ±inf
FTAN Source is ±inf
9.7.3.1 MASKABLE EXCEPTION CONDITIONS. All conditions apply as listed in Table
9-11, with the exception of the FMOVE to byte, word, or long-word case.
a. If the user OPERR exception handler is disabled, an extended-precision
nonsignaling NAN with all mantissa bits set is stored in the destination floating-point
data register. No exceptions are reported, and instruction execution proceeds
normally.
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