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MOTOROLA M68040 USER’S MANUAL 9- 25
the MC68040 does not directly support packed decimal real operands, the processor
never sets INEX1 bit in the FPSR EXC byte, but provides it as a latch so that emulation
software can report the exception.
A floating-point arithmetic exception is taken in one of two situations. The first situation
occurs when the user program enables an arithmetic exception by setting a bit in the
FPCR ENABLE byte and the corresponding bit in the FPSR EXC byte matches the bit in
the FPCR ENABLE byte as a result of program execution; this is referred to as maskable
exception conditions. A user write operation to the FPSR, which sets a bit in the EXC byte,
does not cause an exception to be taken, regardless of the value in the ENABLE byte.
When a user writes to the ENABLE byte that enables a class of floating-point exceptions,
a previously generated floating-point exception does not cause an exception to be taken,
regardless of the value in the FPSR EXC byte. The user can clear a bit in the FPCR
ENABLE byte, disabling each corresponding exception.
The second situation occurs when the processor encounters a nonmaskable SNAN,
OPERR, OVFL, and UNFL condition; this is referred to as nonmaskable exception
conditions. This allows a supervisor exception handler to correct a defaulting result
generated by the MC68040 that is different from the result generated by an
MC68881/MC68882 executing the same code. After correcting the result, the supervisor
exception handler calls a user-defined exception handler if the exception has been
enabled in the FPCR ENABLE byte or returns to the main program flow if the exception is
disabled.
A single instruction execution can generate dual and triple exceptions. When multiple
exceptions occur with exceptions enabled for more than one exception class, the highest
priority exception is reported; the lower priority exceptions are never reported or taken.
The previous list of arithmetic floating-point exceptions is in order of priority. The bits of
the ENABLE byte are organized in decreasing priority, with bit 15 being the highest and bit
8 the lowest. The exception handler must check for multiple exceptions. The address of
the exception handler is derived from the vector number corresponding to the exception.
The following is a list of multiple instruction exceptions that can occur:
SNAN and INEX1
OPERR and INEX2
OPERR and INEX1
OVFL and INEX2 and/or INEX1
UNFL and INEX2 and/or INEX1
9.7.1 Branch/Set On Unordered (BSUN)
The BSUN exception is the result of performing an IEEE nonaware conditional test
associated with the FBcc, FDBcc, FTRAPcc, and FScc instructions when an unordered
condition is present. Refer to 9.5.2 Conditional Testing for information on conditional
tests.
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