Loading...
1- 4 M68040 USER’S MANUAL MOTOROLA
more common case of the branch taken, and both execution paths of the branch are
fetched and decoded to minimize refilling of the instruction pipeline.
DECODE
EA
CALCULATE
WRITE-
BACK
INTEGER
UNIT
CONVERT
EXECUTE
WRITE-
BACK
INSTRUCTION
ATC
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
BUS
CONTROL
SIGNALS
DATA
BUS
ADDRESS
BUS
DATA
ATC
DATA
MMU/CACHE/SNOOP
CONTROLLER
OPERAND DATA BUS
INSTRUCTION DATA BUS
INSTRUCTION
CACHE
DATA
CACHE
FLOATING-
POINT
UNIT
DATA MEMORY UNIT
INSTRUCTION MEMORY UNIT
B
U
S
C
O
N
T
R
O
L
L
E
R
INSTRUCTION
ADDRESS
DATA
ADDRESS
INSTRUCTION
FETCH
EXECUTE
EA
FETCH
Figure 1-1. Block Diagram
To improve memory management, the M68040 includes separate, independent paged
MMUs for instruction and data accesses. Each MMU stores recently used address
mappings in separate 64-entry address translation caches (ATCs). Each MMU also has
two transparent translation registers that define a one-to-one mapping for address space
segments ranging in size from 16 Mbytes to 4 Gbytes each.
Two memory units independently interface with the IU and FPU. Each unit consists of an
MMU, an ATC, a main cache, and a snoop controller. The MMUs perform memory
management on a demand-page basis. By translating logical-to-physical addresses using
translation tables stored in memory, the MMUs support virtual memory systems. Each
MMU stores recently used address mappings in an ATC, reducing the average translation
time.
Separate on-chip instruction and data caches operate independently and are accessed in
parallel with address translation. The caches improve the overall performance of the
system by reducing the number of bus transfers required by the processor to fetch
information from memory and by increasing the bus bandwidth available for alternate bus
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com