9.5.1 Underflow, Round, Overflow
During the calculation of an arithmetic result, the FPU arithmetic logic unit (ALU) has more
precision and range than the 80-bit extended-precision format. However, the final result of
these operations is an extended-precision floating-point value. In some cases, an
intermediate result becomes either smaller or larger than can be represented in extended
precision. Also, the operation can generate a larger exponent or more bits of precision
than can be represented in the chosen rounding precision. For these reasons, every
arithmetic instruction ends by rounding the result and checking for overflow and underflow.
At the completion of an arithmetic operation, the intermediate result is checked to see if it
is too small to be represented as a normalized number in the selected precision. If so, the
UNFL-bit is set in the FPSR EXC byte. The MC68040 then takes a nonmaskable
underflow exception and executes the M68040FPSP underflow exception handler,
denormalizing the result. Denormalizing a number causes a loss of accuracy, but a zero is
not returned unless absolutely necessary. If a number has grossly underflowed, the
M68040FPSP returns a zero or the smallest denormalized number with the correct sign,
depending on the rounding mode in effect.
If no underflow occurs, the intermediate result is rounded according to the user-selected
rounding precision and rounding mode. After rounding, the INEX2-bit of the FPSR EXC
byte is set accordingly. Finally, the magnitude of the result is checked to see if it is too
large to be represented in the current rounding precision. If so, the OVFL-bit of the FPSR
EXC byte is set. The M68040FPSP returns a correctly signed infinity or a correctly signed
largest normalized number, depending on the rounding mode in effect.
9.5.2 Conditional Testing
Unlike the integer arithmetic condition codes, an instruction either always sets the floating-
point condition codes in the same way or it does not change them at all. Therefore, the
instruction descriptions do not include floating-point condition code settings. The following
paragraphs describe how floating-point condition codes are set for all instructions that
modify condition codes. Refer to Floating-Point Condition Code Byte for a
description of the FPCC byte.
The condition code bits differ slightly from the integer condition codes. Unlike the
operation-type-dependent integer condition codes, examining the result at the end of the
operation sets or clears the floating-point condition codes accordingly. The M68000 family
integer condition codes bits N and Z have this characteristic, but the V and C bits are set
differently for different instructions. The data type of the operation’s result determines how
the four condition code bits are set. Table 9-7 lists the condition code bit setting for each
data type. The MC68040 generates only eight of the 16 possible combinations. Loading
the FPCC with one of the other combinations and executing a conditional instruction can
produce an unexpected branch condition.
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