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9- 12 M68040 USER’S MANUAL MOTOROLA
MC68040 produces the same results as any other device that conforms to the IEEE 754
standard but does not support extended precision. The results are the same when
performing the same operation in extended precision and storing the results in single- or
double-precision format.
The FPU performs all floating-point internal operations in extended precision. It supports
mixed-mode arithmetic by converting single- and double-precision operands to extended-
precision values before performing the specified operation. The FPU converts all memory
data formats to extended-precision before using it in a floating-point operation or loading it
in a floating-point data register. The FPU also converts extended-precision data formats in
a floating-point data register to any data format and either stores it in a memory
destination or in an integer data register.
If the external operand is a denormalized number, the number is normalized before an
operation is performed. However, an external denormalized number moved into a floating-
point data register is stored as a denormalized number.
If an external operand is an unnormalized number, the number is normalized before it is
used in an arithmetic operation. If the external operand is an unnormalized zero (i.e., with
a mantissa of all zeros), the number is converted to a normalized zero before the specified
operation is performed. The regular use of unnormalized inputs not only defeats the
purpose of the IEEE 754 standard, but also can produce gross inaccuracies in the results.
9.4.1 Intermediate Result
Figure 9-7 illustrates the intermediate result format. The intermediate result’s exponent for
some dyadic operations (i.e., multiply and divide) can easily overflow or underflow the 15-
bit exponent of the destination floating-point register. To simplify the overflow and
underflow detection, intermediate results in the FPU maintain a 16-bit, twos-complement
integer exponent. Detection of an overflow or underflow intermediate result always
converts the 16-bit exponent into a 15-bit biased exponent before being stored in a
floating-point data register. The FPU internally maintains the 67-bit mantissa for rounding
purposes. The mantissa is always rounded to 64 bits (or less, depending on the selected
rounding precision) before it is stored in a floating-point data register.
16-BIT EXPONENT 63-BIT FRACTION
LSB OF FRACTION
GUARD BIT
ROUND BIT
STICKY BIT
INTEGER BIT
OVERFLOW BIT
Figure 9-7. Intermediate Result Format
If the destination is a floating-point data register, the result is in the extended-precision
format and is rounded to the precision specified by the FPSR PREC bits before being
stored. All mantissa bits beyond the selected precision are zero. If the single- or double-
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