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MOTOROLA M68040 USER’S MANUAL 1- 3
1.2 FEATURES
The main features of the M68040 are as follows:
6-Stage Pipeline, MC68030-Compatible IU
MC68881/MC68882-Compatible FPU
Independent Instruction and Data MMUs
Simultaneously Accessible, 4-Kbyte Physical Instruction Cache and 4-Kbyte Physical
Data Cache
Low-Latency Bus Accesses for Reduced Cache Miss Penalty
Multimaster/Multiprocessor Support via Bus Snooping
Concurrent IU, FPU, MMU, and Bus Controller Operation Maximizes Throughput
32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
User Object-Code Compatible with All Earlier M68000 Microprocessors
4-Gbyte Direct Addressing Range
Software Support Including Optimizing C Compiler and UNIX® System V Port
The on-chip FPU and large physical instruction and data caches yield improved system
performance and increased functionality. The independent instruction and data MMUs and
increased internal parallelism also improve performance.
1.3 EXTENSIONS TO THE M68000 FAMILY
The M68040 is compatible with the ANSI/IEEE
Standard 754 for Binary Floating-Point
Arithmetic
. The MC68040’s FPU has been optimized to execute the most commonly used
subset of the MC68881/MC68882 instruction sets and includes additional instruction
formats for single- and double-precision rounding results. Software emulates floating-point
instructions not directly supported in hardware. Refer to Appendix E M68040 Floating-
Point Emulation (MC68040FPSP) for details on software emulation. The MOVE16 user
instruction is new to the instruction set, supporting efficient 16-byte memory-to-memory
data transfers.
1.4 FUNCTIONAL BLOCKS
Figure 1-1 illustrates a simplified block diagram of the MC68040. Refer to Appendix A
MC68LC040 for information on the MC68LC040’s and MC68040V's functional blocks; and
Appendix B MC68EC040 for information on the MC68EC040’s and MC68EC040V's
functional blocks.
The M68040 IU pipeline has been expanded from the MC68030 to include effective
address calculation (<ea> calculate) and operand fetch (<ea> fetch) stages with
commonly used effective addressing modes. Conditional branches are optimized for the
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