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9- 4 M68040 USER’S MANUAL MOTOROLA
15 14
EXCEPTION ENABLE
12 11 10 9 8
INEXACT DECIMAL INPUT
INEXACT OPERATION
DIVIDE BY ZERO
UNDERFLOW
OVERFLOW
OPERAND ERROR
SIGNALING NOT-A-NUMBER
BRANCH/SET ON UNORDERED 
7 65432 1 0
SNAN
OPERR
OVFL UNFL DZ INEX2 INEX1BSUN PREC RND 0
ROUNDING PRECISION
ROUNDING MODE
MODE CONTROL
13
Figure 9-2. Floating-Point Control Register
9.2.3 Floating-Point Status Register (FPSR)
The FPSR (see Figure 9-1) contains a floating-point condition code (FPCC) byte, a
quotient byte, a floating-point exception status byte (EXC), and a floating-point accrued
exception byte (AEXC). The user can read or write to all bits in the FPSR. Execution of
most floating-point instructions modifies this register. The reset function or a restore
operation of the null state clears the FPSR. Floating-point conditional operations are not
guaranteed if the FPSR is written directly, because the FPSR is only valid as a result of a
floating-point instruction.
9.2.3.1 FLOATING-POINT CONDITION CODE BYTE. The FPCC byte (see Figure 9-3)
contains four condition code bits that are set at the end of all arithmetic instructions
involving the floating-point data registers. These bits are sign of mantissa (N), zero (Z),
infinity (I), and NAN. The FMOVE FPm,<ea>, FMOVEM FPm, and FMOVE FPCR
instructions do not affect the FPCC.
NZI NAN
31 30 29 28 27 26 25 24
NOT-A-NUMBER OR UNORDERED
INFINITY
ZERO
NEGATIVE
0
Figure 9-3. FPSR Condition Code Byte
To aid programmers of floating-point subroutine libraries, the MC68040 implements the
four FPCC bits in hardware instead of only implementing the four IEEE conditions. An
instruction derives the IEEE conditions when needed. For example, the programmers of a
complex arithmetic multiply subroutine usually prefer to handle special data types such as
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