exception instead of executing the exception handler for the original exception
condition. For example, if simultaneous interrupt and trap exceptions are pending, the
exception processing for the trap exception occurs first, followed immediately by
exception processing for the interrupt. When the processor resumes normal
instruction execution, it is in the interrupt handler, which returns to the trap exception
Exception processing for access error exceptions creates a format $7 stack frame
that contains status information that can indicate a pending trace, floating-point post-
instruction, or unimplemented floating-point instruction exception. The RTE instruction
used to return from the access error exception handler checks the status bits for one
of these pending exceptions. If one is indicated, the RTE changes the access error
stack frame to match the pending exception and fetches the vector for the exception.
Instruction execution then resumes in the new exception handler.
If an access error, trace, and one of the two (mutually exclusive) floating-point
exceptions occur simultaneously, the pending floating-point exception is indicated in
the access error stack and the trace exception flag is undefined. The exception
handler for the floating-point exception must check the trace bits on the stack and call
the trace handler directly (after adjusting the stack frame to match the format for the
trace exception).
If a trace exception is pending at the same time an exception priority level 3 or
floating-point post-instruction exception is pending, the trace exception is not
reported, and the exception handler for the other exception condition must check for
the trace condition.
After the processor has completed executing the exception handlers for all pending
exceptions, the processor resumes normal instruction execution at the address in the
processor’s vector table for the last exception processed. Once the exception handler has
completed execution, if possible the processor must return the system context as it was
prior to the exception using the RTE instruction. (If the internal data of the exception stack
frames are manipulated, M68040 may enter into an undefined state; this applies
specifically to the SSW on the access error stack frame.)
When the processor executes an RTE instruction, it examines the stack frame on top of
the active supervisor stack to determine if it is a valid frame and what type of context
restoration it requires. If during restoration, a stack frame has an odd address PC and an
SR that indicates user trace mode enabled, then an address error is taken. The SR
stacked for the address error has the SR S-bit set. For previous members of the M68000
family the S-bit is clear. When the M68040 writes or reads a stack frame, it uses long-
word operand transfers wherever possible. Using a long-word-aligned stack pointer
greatly enhances exception processing performance. The processor does not necessarily
read or write the stack frame data in sequential order. The system software should not
depend on a particular exception generating a particular stack frame. For compatibility
with future devices, the software should be able to handle any format of stack frame for
any type of exception. The following paragraphs discuss in detail each stack frame format.
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