8.2.10 Reset Exception
Asserting the reset in (RSTI) input signal causes a reset exception. The reset exception
has the highest priority of any exception; it provides for system initialization and recovery
from catastrophic failure. Reset also aborts any processing in progress when RSTI is
recognized; processing cannot be recovered. Figure 8-5 is a flowchart of the reset
exception processing.
The reset exception places the processor in the interrupt mode of the supervisor privilege
mode by setting the S-bit and clearing the M-bit and disables tracing by clearing the T1
and T0 bits in the SR. This exception also sets the processor’s interrupt priority mask in
the SR to the highest level, level 7. Next the VBR is initialized to zero ($00000000), and
the enable bits in the cache control register (CACR) for the on-chip caches are cleared.
The reset exception also clears the enable bit but does not affect page size in the
translation control registers. It clears the enable bit in each of the four transparent
translation registers. An interrupt acknowledge bus cycle is begun to generate a vector
number. This vector number references the reset exception vector (two long words, vector
numbers 0 and 1) at offset zero in the supervisor address space. The first long word is
loaded into the interrupt stack pointer, and the second long word is loaded into the PC.
Reset exception processing concludes with the prefetch of the first four long words
beginning at the memory location pointed to by the PC.
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