8.2.8 Breakpoint Instruction Exception
To use the M68040 in a hardware emulator, the processor must provide a means of
inserting breakpoints in the emulator code and performing appropriate operations at each
breakpoint. Inserting an illegal instruction at the breakpoint and detecting the illegal
instruction exception from its vector location can achieve this. However, since the VBR
allows arbitrary relocation of exception vectors, the exception address cannot reliably
identify a breakpoint. Consequently, the processor provides a breakpoint capability with a
set of breakpoint exceptions, $4848–$484F.
When the M68040 executes a breakpoint instruction, it performs a breakpoint
acknowledge cycle (read cycle) with an acknowledge transfer type and transfer modifier
value of $0. Refer to Section 7 Bus Operation for a description of the breakpoint
acknowledge cycle. After external hardware terminates the bus cycle with either TA or
TEA, the processor performs illegal instruction exception processing.
8.2.9 Interrupt Exception
When a peripheral device requires the services of the M68040 or is ready to send
information that the processor requires, it can signal the processor to take an interrupt
exception using the active-low IPL2IPL0 signals. The three signals encode a value of 0–7
(IPL0 is the least significant bit). High levels on all three signals correspond to no interrupt
requested (level 0). Values 1–7 specify one of seven levels of interrupts, with level 7
having the highest priority. Table 8-3 lists the interrupt levels, the states of IPL2IPL0 that
define each level, and the SR interrupt mask value that allows an interrupt at each level.
Table 8-3. Interrupt Levels and Mask Values
Requested Control Line Status Interrupt Mask Level
Interrupt Level Required for Recognition
0 High High High No Interrupt Requested
1 High High Low 0
2 High Low High 0–1
3 High Low Low 0–2
4 Low High High 0–3
5 Low High Low 0–4
6 Low Low High 0–5
7 Low Low Low 0–7
When an interrupt request has a priority higher than the value in the interrupt priority mask
of the SR (bits 10–8), the processor makes the request a pending interrupt. Priority level
7, the nonmaskable interrupt, is a special case. Level 7 interrupts cannot be masked by
the interrupt priority mask, and they are transition sensitive. The processor recognizes an
interrupt request each time the external interrupt request level changes from some lower
level to level 7, regardless of the value in the mask. Figure 8-3 shows two examples of
interrupt recognitions, one for level 6 and one for level 7. When the M68040 processes a
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