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MOTOROLA M68040 USER’S MANUAL 8- 11
Table 8-2. Tracing Control
T1 T0 Tracing Function
0 0 No Tracing
0 1 Trace on Change of Flow
1 0 Trace on Instruction Execution (Any Instruction)
1 1 Undefined, Reserved
When the processor is in the trace mode and attempts to execute an illegal or
unimplemented instruction, that instruction does not cause a trace exception since the
instruction is not executed. This is of particular importance to an instruction emulation
routine that performs the instruction function, adjusts the stacked PC to skip the
unimplemented instruction, and returns. Before returning, the trace bits of the SR on the
stack should be checked. If tracing is enabled, the trace exception processing should also
be emulated for the trace exception handler to account for the emulated instruction.
Trace exception processing starts at the end of normal processing for the traced
instruction and before the start of the next instruction. As illustrated in Figure 8-1, the
processor makes an internal copy of the SR, and enters the supervisor mode. It also
clears the T1 and T0 bits of the SR, disabling further tracing. The processor supplies
vector number 9 for the trace exception and saves the trace exception vector offset, PC
value, and the internal copy of the SR on the supervisor stack. The saved value of the PC
is the logical address of the next instruction to be executed. Instruction execution resumes
after the required prefetches from the address in the trace exception vector.
When the STOP instruction is traced, the processor never enters the stopped condition. A
STOP instruction that begins execution with the trace bits equal to $3 forces a trace
exception after it loads the SR. Upon return from the trace exception handler, execution
continues with the instruction following the STOP instruction, and the processor never
enters the stopped condition.
8.2.7 Format Error Exception
Just as the processor checks for valid prefetched instructions, it also performs some
checks of data values for control operations. The RTE instruction checks the validity of the
stack format code. For floating-point unit (FPU) state frames, the FRESTORE instruction
compares the internal version number of the processor to that contained in the state frame
(refer to Section 9 Floating-Point Unit (MC68040 Only)). This check ensures that the
processor can correctly interpret internal FPU state information from the state frame. If
any of these checks determine that the format of the data is improper, the instruction
generates a format error exception. This exception saves a stack frame, generates
exception vector number 14, and continues execution at the address in the format
exception vector. The stacked PC value is the logical address of the instruction that
detected the format error.
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