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8- 8 M68040 USER’S MANUAL MOTOROLA
does not attempt to alter the current state of memory. Only an external reset can restart a
processor halted by a double bus fault.
The supervisor stack has special requirements to ensure that exceptions can be stacked.
The stack must be resident with correct protection in the direction of growth to ensure that
exception stacking never has a bus error or internal access fault. Memory pages allocated
to the stack that are higher in memory than the current stack pointer can be nonresident
since an RTE or FRESTORE instruction can check for residency and trap before restoring
the state.
A special case exists for systems that allow arbitration of the processor bus during locked
transfer sequences. If the arbiter can signal a bus error of a locked translation table
update due to an improperly broken lock, any pages touched by exception stack
operations must have the U-bit set in the corresponding page descriptor to prevent the
occurrence of the locked access during translation table searches.
8.2.2 Address Error Exception
An address error exception occurs when the processor attempts to prefetch an instruction
from an odd address. This includes the case of a conditional branch instruction with an
odd branch offset that is not taken. A prefetch bus cycle is not executed, and the
processor begins exception processing after the currently executing instructions have
completed. If the completion of these instructions generates another exception, the
address error exception is deferred, and the new exception is serviced. After exception
processing for the address error exception commences, the sequence is the same as an
access fault exception, except that the vector number is 3 and the vector offset in the
stack frame refers to the address error vector. The stack frame is generated containing
the address of the instruction that caused the address error and the address itself (A0 is
cleared). If an address error occurs during the exception processing for a bus error,
address error, or reset, a double bus fault occurs.
8.2.3 Instruction Trap Exception
Certain instructions are used to explicitly cause trap exceptions. The TRAP#n instruction
always forces an exception and is useful for implementing system calls in user programs.
The TRAPcc, FTRAPcc, TRAPV, CHK, and CHK2 instructions force exceptions if the user
program detects an error, which can be an arithmetic overflow or a subscript value that is
out of bounds. The DIVS and DIVU instructions force exceptions if a division operation is
attempted with a divisor of zero.
As illustrated in Figure 8-1, when a trap exception occurs, the processor internally copies
the SR, enters the supervisor mode, and clears T1 and T0. The processor generates a
vector number according to the instruction being executed. Vector 5 is for DIVx, vector 6 is
for CHK and CHK2, and vector 7 is for FTRAPcc, TRAPcc, and TRAPV instructions. For
the TRAP#n instruction, the vector number is 32 plus n. The stack frame saves the trap
vector offset, the PC, and the internal copy of the SR on the supervisor stack. The saved
value of the PC is the logical address of the instruction following the instruction that
caused the trap. For all instruction traps other than TRAP#n, a pointer to the instruction
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