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xxii M68040 USER’S MANUAL MOTOROLA
LIST OF TABLES
Table Page
Number Title Number
1-1 M68040 Data Formats ................................................................................. 1-9
1-2 Effective Addressing Modes ........................................................................ 1-10
1-3 Notational Conventions ................................................................................ 1-11
1-4 Instruction Set Summary.............................................................................. 1-14
3-1 Updating U-Bit and M-Bit for Page Descriptors............................................ 3-22
3-2 SFC and DFC Values................................................................................... 3-22
4-1 Snoop Control Encoding .............................................................................. 4-9
4-2 TLNx Encoding ............................................................................................ 4-11
4-3 Instruction-Cache Line State Transitions ..................................................... 4-15
4-4 Data-Cache Line State Transitions .............................................................. 4-17
5-1 Signal Index ................................................................................................. 5-2
5-2 Transfer-Type Encoding .............................................................................. 5-5
5-3 Normal and MOVE16 Access Transfer Modifier Encoding .......................... 5-6
5-4 Alternate Access Transfer Modifier Encoding .............................................. 5-6
5-5 Output Driver Control Groups ...................................................................... 5-11
5-6 Processor Status Encoding .......................................................................... 5-13
5-7 Signal Summary........................................................................................... 5-16
6-1 IEEE Standard 1149.1A Instructions ........................................................... 6-3
6-2 Boundary Scan Bit Definitions ..................................................................... 6-10
7-1 Data Bus Requirements for Read and Write Cycles .................................... 7-4
7-2 Summary of Access Types versus Bus Signal Encodings........................... 7-6
7-3 Memory Alignment Influence on Noncachable and
Write-Through Bus Cycles ......................................................................... 7-9
7-4 Interrupt Acknowledge Termination Summary ............................................. 7-31
7-5 TA and TEA Assertion Results ..................................................................... 7-37
7-6 M68040 Bus Arbitration States .................................................................... 7-48
8-1 Exception Vector Assignments .................................................................... 8-5
8-2 Tracing Control ............................................................................................ 8-11
8-3 Interrupt Levels and Mask Values................................................................ 8-12
8-4 Exception Priority Groups ............................................................................ 8-19
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