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MOTOROLA M68040 USER’S MANUAL 7- 69
BCLK
SIZ1, SIZ0
TT1, TT0
TM2–TM0
D31–D0
UPA1, UPA0
CIOUT
TS
TIP
TA
R/W
C1 C2 C3 C4 C5
A31–A0
TLN1, TLN0
NOTE: The selected device increments the value of A3 and A2.
10 11 0001
A1, A0 =
Figure 7-46. Multiplexed Address and Data Bus (Line Write)
7.11.3 Data Latch Enable Mode
The data latch enable (DLE) mode allows read data to be latched by the assertion of the
DLE signal instead of by the BCLK rising edge at the end of each transfer. In some
applications, this mode can reduce the number of clocks required to perform line burst
reads. A logic zero on the MDIS enables this mode during a processor reset.
Figure 7-47 illustrates a conceptual block diagram of the logic used to latch the read data
bus in DLE mode. The DLE signal controls transparent latch A, which allows data to be
latched before the rising edge of BCLK. Latch A operates transparently when DLE is
negated and latches the level on the data bus when DLE is asserted. Note that the DLE
signal only controls latching of the read data and does not affect termination of the bus
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