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7- 66 M68040 USER’S MANUAL MOTOROLA
should not exceed VCC while it is ramping up. RSTI is internally synchronized for two
BCLKS before being used and must meet the specified setup and hold times to BCLK
(specifications #51 and #52 in Section 11 MC68040 Electrical and Thermal
Characteristics) only if recognition by a specific BCLK rising edge is required. MI is
asserted while the M68040 is in reset.
BCLK
BUS
SIGNALS
+5 V
0 V
RSTI
TS
BR
CDIS, MDIS,
IPL2–IPL0
BG
BB
TIP
VCC
Undefined
t 10
CLOCKS
2
CLOCKS
128
CLOCKS
>
MI
Figure 7-44. Initial Power-On Reset Timing
Once RSTI negates, the processor is internally held in reset for another 128 clock cycles.
During the reset period, all signals that can be, are three-stated, and the rest are driven to
their inactive state. Once the internal reset signal negates, all bus signals continue to
remain in a high-impedance state until the processor is granted the bus. Afterwards, the
first bus cycle for reset exception processing begins. In Figure 7-44 the processor
assumes implicit bus ownership before the first bus cycle begins. The levels on CDIS,
MDIS, and IPL2–IPL0 are used to selectively enable the special modes of operation when
RSTI is negated. These signals should be driven to their normal levels before the end of
the 128-clock internal reset period.
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