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MOTOROLA M68040 USER’S MANUAL 7- 65
A31–A0
BCLK
D31–D0
TS
TA
ALTERNATE MASTER
LONG-WORD WRITE
BR
BG
BB
PROCESSOR
SC1, SC0
SIZ1, SIZ0
TT1, TT0
R/W
MI
C1 C2 C3 C4 C5 C6
TA DRIVEN BY PROCESSOR
MEMORY INHIBITED FROM RESPONDING
DATA WRITTEN BY ALTERNATE BUS MASTER
AM_BR
AM_BG
*
*
*AM indicates the alternate bus master.
Figure 7-43. Snooped Long-Word Write, Memory Inhibited
7.10 RESET OPERATION
An external device asserts the reset input signal (RSTI) to reset the processor. When
power is applied to the system, external circuitry should assert RSTI for a minimum of 10
BCLK cycles after VCC is within tolerance. Figure 7-44 is a functional timing diagram of
the power-on reset operation, illustrating the relationships among VCC, RSTI, mode
selects, and bus signals. The BCLK and PCLK clock signals are required to be stable by
the time VCC reaches the minimum operating specification. The VIH levels of the clocks
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