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7- 62 M68040 USER’S MANUAL MOTOROLA
illustrated, which results in a memory access having the equivalent of two wait states.
Variations in the timing required by snooping logic to access the caches can delay the
negation of MI by up to two additional clocks. External logic must ensure that the
termination signals negate at all rising BCLK edges in which MI is asserted. Otherwise, if
one of the termination signals is asserted, either the M68040 ignores all termination
signals, reading them as negated, or the M68040 exhibits improper operation.
A31–A0
BCLK
D31–D0
TS
TA
ALTERNATE
MASTER
BR
BG
BB
AM_BR
AM_BG
PROCESSOR
SC1–SC0
SIZ1, SIZ0
TT1, TT0
R/W
MI
C1 C2 C3 C4 C5 C6
Undefined
*
*
AM indicates the alternate bus master.
*
Figure 7-41. Snoop Access with Memory Response
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