7.9.1 Snoop-Inhibited Cycle
For alternate bus master accesses in which the SCx signal encodings indicate that
snooping is inhibited (SCx = $0), the M68040 immediately negates MI and allows memory
to respond to the access. Snoop-inhibited alternate bus master accesses do not affect
performance of the processor since no cache lookups are required. Figure 7-40 illustrates
an example of a snoop-inhibited operation in which an alternate bus master is granted the
bus for an access. No matter what the values are on the SCx and TTx signals, MI is
asserted between bus cycles. Because MI is asserted while a cache lookup is performed,
snooping inherently degrades system performance.
MI is asserted from the last TA of the current bus cycle if the M68040 owns the bus and
loses it (see Figure 7-40). If an alternate bus master has the bus and loses it, there are
two different resulting cases. Usually, an idle clock occurs between the alternate bus
master’s cycle and the MC68040’s cycle. If so, MI is asserted during the idle clock and
negated from the same edge that the M68040 asserts the TS signal (see Figure 7-40). If
there is no idle clock, MI is not asserted. MI is asserted during and after reset until the first
bus cycle of the M68040. Even though snoop is inhibited, all TA or TEA assertions while
MI is asserted are ignored. If a line snoop is started, the M68040 still requires four TA
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