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7- 58 M68040 USER’S MANUAL MOTOROLA
AM_BG*,
040_BG
040_BG*,
AM_BG*
R Λ RV Λ A* Λ
AV V AV* V RV*
R* V RV* V
R Λ RV Λ LOCK Λ
LOCKE*
R Λ RV Λ LOCK Λ
LOCKE V R Λ RV Λ
LOCK*
LOCK Λ LOCKE*
LOCKE 
V LOCK*
R* Λ RV Λ A* Λ
AV V A Λ AV
S1
S2
S3
S4
S5
S6
R* Λ RV Λ A Λ AV
V RV* V RA*
R* Λ RV Λ A* Λ AV
R Λ RV
RV* V RA* V
R Λ RV Λ A Λ AV
R Λ RV Λ A* Λ AV
R* Λ RV
(a) MC68040 Low-Priorty, Default Bus Master
040_BG*,
AM_BG
040_BG*,
AM_BG
040_BG*,
AM_BG*
040_BG*,
AM_BG*
040_BG*,
AM_BG
040_BG*,
AM_BG
AM_BG*,
040_BG
040_BG*,
AM_BG*
R* Λ RV Λ A* Λ AV
V R Λ RV Λ 040_BR
R* V RV* V 040_BR
R Λ RV Λ 040_BR
040_BR R* Λ RV Λ A* Λ AV
V A Λ AV
S1
S2
S3
S4
S5
S6
R Λ RV Λ 040_BR
R Λ RV Λ A* Λ AV
R* Λ RV
1. It is assumed that the asynchronous device takes the bus only after TIP or the MC68040's BB is negated.
040_BG*,
AM_BG
040_BG*,
AM_BG
040_BG*,
AM_BG*
040_BG*,
AM_BG*
040_BG*,
AM_BG
040_BG*,
AM_BG
040_BR
R* Λ RV Λ A* Λ AV
V AV* V RV*
(b) MC68040 High-Priorty, Default Bus Master
RV* V RA* V
R Λ RV Λ A Λ AV
R* Λ RV Λ A Λ AV
V RV* V RA*
NOTES:
2. *Indicates the signal is asserted for that device.
Figure 7-39. M68040 Asynchronous DMA Arbitration
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