give the bus to processor 2. The arbiter remains in state B until BB is negated,
signifying the end of the bus cycle.
Once state C is reached, depending on whether or not processor 2 asserts BR2 and then
negates BR2 because of a disregard request condition, processor 1 may or may not
actively begin a bus cycle. If no other bus requests are pending by the time state C is
reached, processor 2 is in the implicit ownership state. If processor 1 asserts BR1, then it
is possible for state C to persist for only one clock. In this case, processor 2 does not have
a chance to run any active bus cycles.
A null bus cycle tenure is better than having the external bus arbiter wait for processor 2 to
perform at least one bus cycle before returning bus ownership to processor 1, even
though this appears to be a waste of bus arbitration overhead. Note that once processor 2
enters the disregard request condition, processor 2 reasserts BR anywhere from one clock
to an undetermined number of clocks before running another bus cycle. Waiting for
processor 2 to run a bus cycle can result in a temporary bus arbitration lockup.
This bus arbitration scheme is restricted if the system supports the relinquish and retry
operation that can occur for the last write cycle of a locked transfer. In this case, LOCKE
cannot be used. Assuming that LOCKE is always negated excludes the need for LOCKE in
an arbitration similar to this example. The reason for this restriction is that the external bus
arbiter gives up the bus to the other processor once LOCKE is asserted. If a relinquish and
retry operation were to occur, then the next bus cycle would be from the other processor
violating the integrity of the locked transfer. DUAL M68040 PRIORITIZED ARBITRATION. This example is very similar to the
dual M68040 fairness arbitration example, except that one processor is assigned higher
priority over the other. Processor 2 can own the bus only if there are no processor 1
pending requests. It is important to note that when the processor asserts the LOCK signal,
it also asserts BR1. This implementation replaces LOCK with BR because BR is more
demanding than using LOCK. Only when processor 2 is in the middle of a locked
operation does it have higher priority than processor 1. Similar to the M68040 fairness
arbitration example, the restriction on using LOCKE applies to this example. Figure 7-36
illustrates the state diagram for dual M68040 prioritized arbitration.
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