MOTOROLA M68040 USER’S MANUAL 7- 49
AM indicates the alternate bus master.
Figure 7-31. Lock Violation Example
In addition to the indeterminate condition, the external arbiter’s design needs to include
the function of BR. For example, in certain cases associated with conditional branches,
the M68040 can assert BR to request the bus from an alternate bus master, then negate
BR without using the bus, regardless of whether or not the external arbiter eventually
asserts BG. This situation happens when the M68040 attempts to prefetch an instruction
for a conditional branch. To achieve maximum performance, the processor prefetches the
instructions of both paths for a conditional branch. If the conditional branch results in a
branch-not-taken, the previously issued branch-taken prefetch is then terminated since the
prefetch is no longer needed. In an attempt to save time, the M68040 negates BR. If BG
takes too long to assert, the M68040 enters a disregard request condition.
The BR signal can be reasserted immediately for a different pending bus request, or it can
stay negated indefinitely. If an external bus arbiter is designed to wait for the M68040 to
assert BB before proceeding, then the system experiences an extended period of time in
which bus arbitration is locked. Motorola recommends that an external bus arbiter not
assume that there is a direct relationship between BR and BB or BR and BG signals.
Figure 7-32 illustrates an example of the processor requesting the bus from the external
bus arbiter. During C1, the M68040 asserts BR to request the bus from the arbiter, which
negates the alternate bus master’s BG signal and grants the bus to the processor by
asserting BG during C3. During C3, the alternate bus master completes its current access
and relinquishes the bus by three-stating all bus signals. Typically, the BB and TIP signals