In the second situation, the processor samples BB until the external bus arbiter negates
BB . The processor drives its output pins with undetermined values and three-states BB,
but does not perform a bus cycle. This procedure, called implicit ownership of the bus,
occurs when the processor is granted the bus but there are no pending bus cycles. If an
internal access request is generated, the processor assumes explicit ownership of the bus
and immediately begins an access, simultaneously asserting BB, BR , TIP, and TS. If the
external arbiter keeps BG asserted after completion of the bus cycle, the processor keeps
BB asserted and drives the bus with undefined values, causing the processor to park. In
this case, because BB remains asserted until the external arbiter negates BG, the
processor must assert BR , TIP, and TS simultaneously to enter an active bus cycle. When
it completes the active bus cycle and the external arbiter has not negated BG, the
processor goes back into park, negating BR, TIP, and TS. As long as BG is asserted, the
processor oscillates between park and active bus cycles.
The M68040 can be in any one of five bus arbitration states during bus operation: idle,
snoop, implicit ownership, park, and active bus cycle. There are two characteristics that
determine these five states: whether the three-state logic determines if the M68040 drives
the bus and how the M68040 drives BB. If neither the processor nor the external bus
arbiter asserts BB, then an external pullup resistor drives BB high to negate it. Note that
the relationship between the internal BR and the external BR is best described as a
synchronous delay off BCLK.
The idle state occurs when the M68040 does not have ownership of the bus and is not in
the process of snooping an access. In the idle state, BB is negated and the M68040 does
not drive the bus. The snoop state is similar to the idle state in that the M68040 does not
have ownership of the bus. The snoop state differs from the idle state in that the M68040
is ready to service snooped transfers. Otherwise, the status of BB and the bus is identical.
The implicit ownership state indicates that the M68040 owns the bus. The M68040
explicitly owns the bus when it runs a bus cycle immediately after being granted the bus. If
the processor has completed at least one bus cycle and no internal transfers are pending,
the processor drives the bus with undefined values, entering the park state. In either case,
BG remains asserted. The simultaneous assertion of BR, TIP, and TS allows the processor
to leave the park state and enter the active bus cycle state.
Figure 7-30 is a bus arbitration state diagram illustrating the relationship of these five
states with an example of an external bus arbiter circuit. Table 7-6 lists the five states and
the conditions that indicate them.
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com