be continuously granted to the processor, and no arbiter is needed. Systems that include
several devices that can become bus masters require an arbiter to assign priorities to
these devices so that, when two or more devices simultaneously attempt to become the
bus master, the one having the highest priority becomes the bus master first.
7.8.1 Bus Arbitration
The M68040 bus controller generates bus requests to the external arbiter in response to
internal requests from the instruction and data memory units. The M68040 performs bus
arbitration using the bus request (BR), bus grant (BG), and bus busy (BB) signals. The
arbitration protocol, which allows arbitration to overlap with bus activity, requires a single
idle clock to prevent bus contention when transferring bus ownership between bus
masters. The bus arbitration unit in the M68040 operates synchronously and transitions
between states on the rising edge of BLCK.
The M68040 requests the bus from the external bus arbiter by asserting BR whenever an
internal bus request is pending. The processor continues to assert BR for as long as it
requires the bus. The processor negates BR at any time without regard to the status of BG
and BB . If the bus is granted to the processor when an internal bus request is generated,
BR is asserted simultaneously with transfer start (TS), allowing the access to begin
immediately. The processor always drives BR , and BR cannot be wire-ORed with other
The external arbiter asserts BG to indicate to the processor that it has been granted the
bus. If BG is negated while a bus cycle is in progress, the processor relinquishes the bus
at the completion of the bus cycle. To guarantee that the bus is relinquished, BG must be
negated prior to the rising edge of the BCLK in which the last TA or TEA is asserted. Note
that the bus controller considers the four bus transfers for a burst-inhibited line transfer to
be a single bus cycle and does not relinquish the bus until completion of the fourth
transfer. The read and write portions of a locked read-modify-write sequence are divisible
in the M68040, allowing the bus to be arbitrated away during the locked sequence. For
system applications that do not allow locked sequences to be broken, the arbiter can use
LOCK to detect locked accesses and prevent the negation of BG to the processor during
these sequences. The processor also provides the LOCKE signal to indicate the last write
cycle of a locked sequence, allowing arbitration between back-to-back locked sequences.
See 7.4.5 Read-Modify-Write Transfers (Locked Transfers) for a detailed description of
read-modify-write transfers.
When the bus has been granted to the processor in response to the assertion of BR, one
of two situations can occur. In the first situation, the processor monitors BB to determine
when the bus cycle of the alternate bus master is complete. After the alternate bus master
negates BB, the processor asserts BB to indicate explicit bus ownership and begins the
bus cycle by asserting TS. The processor continues to assert BB until the external arbiter
negates BG, after which BB is first negated at the completion of the bus cycle, then forced
to a high-impedance state. As long as BG is asserted, BB remains asserted to indicate the
bus is owned, and the processor continuously drives the bus signals. The processor
negates BR when there are no pending accesses to allow the external arbiter to grant the
bus to the alternate bus master if necessary.
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