on the operand read itself can cause the instruction to be aborted, preventing multiple
reads. It is important to note that when memory accesses are serialized noncachable,
FMOVE will cause two identical writes to the same location to occur if the next instruction
prefetch receives a bus error.
Since write cycles can be deferred indefinitely, many subsequent instructions can be
executed, resulting in seemingly nonsequential instruction execution. When this action is
not desired and the system depends on sequential execution following bus activity, the
NOP instruction can be used. The NOP instruction forces instruction and bus
synchronization because it freezes instruction execution until all pending bus cycles have
A write operation of control information to an external register in which the external
hardware attempts to control program execution based on the data that is written with the
conditional assertion of TEA is one situation where the NOP instruction can be used to
prevent multiple executions. If the data cache is enabled and the write cycle results in a hit
in the data cache, the cache is updated. That data, in turn, may be used in a subsequent
instruction before the external write cycle completes. Since the M68040 cannot process
the bus error until the end of the bus cycle, the external hardware cannot successfully
interrupt program execution. To prevent a subsequent instruction from executing until the
external cycle completes, the NOP instruction can be inserted after the instruction causing
the write. In this case, access error exception processing proceeds immediately after the
write before subsequent instructions are executed. This is an irregular situation, and the
use of the NOP instruction for this purpose is not required by most systems.
Note that the NOP instruction can also be used to force access serialization by placing
NOP before the instruction that reads an I/O device. This practice eliminates the need to
specify the entire page as serialized noncachable but does not prevent the instruction
from being aborted by an exception condition.
The bus design of the M68040 provides for one bus master at a time, either the M68040
or an external device. More than one device having the capability to control the bus can
be attached to the bus. An external arbiter prioritizes requests and determines which
device is granted access to the bus. Bus arbitration is the protocol by which the processor
or an external device becomes the bus master. When the M68040 is the bus master, it
uses the bus to read instructions and data not contained in its internal caches from
memory and to write data to memory. When an alternate bus master owns the bus, the
M68040 is able to monitor the alternate bus master’s transfer and intervene when
necessary to maintain cache coherency. This capability is discussed in more detail in 7.9
Bus Snooping Operation.
Unlike earlier members of the M68000 family, the M68040 implements an arbitration
method in which an external arbiter controls bus arbitration and the processor acts as a
slave device requesting ownership of the bus from the arbiter. Since the user defines the
functionality of the external arbiter, it can be configured to support any desired priority
scheme. For systems in which the processor is the only possible bus master, the bus can
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