Loading...
MOTOROLA M68040 USER’S MANUAL xix
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
7-26 Word Write Access Terminated with TEA Timing ........................................ 7-39
7-27 Line Read Access Terminated with TEA Timing .......................................... 7-40
7-28 Retry Read Transfer Timing ......................................................................... 7-41
7-29 Retry Operation on Line Write ...................................................................... 7-42
7-30 M68040 Internal Interpretation State Diagram and
External Bus Arbiter Circuit ........................................................................ 7-47
7-31 Lock Violation Example ................................................................................ 7-49
7-32 Processor Bus Request Timing.................................................................... 7-50
7-33 Arbitration During Relinquish and Retry Timing ........................................... 7-51
7-34 Implicit Bus Ownership Arbitration Timing.................................................... 7-52
7-35 Dual M68040 Fairness Arbitration State Diagram ........................................ 7-53
7-36 Dual M68040 Prioritized Arbitration State Diagram ..................................... 7-55
7-37 M68040 Synchronous DMA Arbitration ........................................................ 7-56
7-38 Sample Synchronizer Circuit ........................................................................ 7-57
7-39 M68040 Asynchronous DMA Arbitration ...................................................... 7-58
7-40 Snoop-Inhibited Bus Cycle ........................................................................... 7-61
7-41 Snoop Access with Memory Response........................................................ 7-62
7-42 Snooped Line Read, Memory Inhibited ........................................................ 7-64
7-43 Snooped Long-Word Write, Memory Inhibited ............................................. 7-65
7-44 Initial Power-On Reset Timing...................................................................... 7-66
7-45 Normal Reset Timing ................................................................................... 7-67
7-46 Multiplexed Address and Data Bus (Line Write)........................................... 7-69
7-47 DLE Mode Block Diagram ............................................................................ 7-70
7-48 DLE versus Normal Data Read Timing ........................................................ 7-71
8-1 General Exception Processing Flowchart .................................................... 8-3
8-2 General Form of Exception Stack Frame ..................................................... 8-4
8-3 Interrupt Recognition Examples ................................................................... 8-14
8-4 Interrupt Exception Processing Flowchart .................................................... 8-16
8-5 Reset Exception Processing Flowchart........................................................ 8-18
8-6 Flowchart of RTE Instruction for Throwaway Four-Word Frame .................. 8-22
8-7 Special Status Word Format ........................................................................ 8-24
8-8 Write-Back Status Format ............................................................................ 8-26
9-1 Floating-Point User Programming Model ..................................................... 9-2
9-2 Floating-Point Control Register .................................................................... 9-4
9-3 FPSR Condition Code Byte.......................................................................... 9-4
9-4 FPSR Quotient Byte ..................................................................................... 9-5
9-5 FPSR Exception Status Byte ....................................................................... 9-5
9-6 FPSR Accrued Exception Byte .................................................................... 9-6
9-7 Intermediate Result Format.......................................................................... 9-12
9-8 Rounding Algorithm Flowchart ..................................................................... 9-14
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com