buffer into the cache to eliminate an unnecessary push access. If a bus error occurs
during a data cache push, the corresponding cache line remains valid (with the new line
data) if the line push follows a replacement line read, or is invalidated if a CPUSH
instruction explicitly forces the push. Write accesses to memory pages specified as write-
through by the data memory unit update the corresponding cache line before accessing
memory. If a bus error occurs during a memory access, the cache line remains valid with
the new data. Figure 7-26 illustrates a functional timing diagram of a bus error on a word
write access causing an access error exception. Figure 7-27 illustrates a functional timing
diagram of a bus error on a line read access that does not cause an access error
A physical bus error during an FSAVE instruction results in corruption of the floating-point
state frame. This is not a serious limitation since, prior to writing the stack frame, the
M68040 ensures that the pages required for the floating-point state frame are resident.
Therefore, only a physical bus error can cause an access error during the stacking of the
state frame. In a normal application, writes caused by the processor should not result in a
physical bus error since the logical address space has already been translated and
allocated. Since there should be no parity errors caused by processor write accesses, only
spurious assertions of the TEA pin can cause physical bus errors. Furthermore, because
FSAVE instructions usually place the state frame on the system stack, the occurrence of a
physical bus error when using the system stack indicates a serious hardware error.
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com