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MOTOROLA M68040 USER’S MANUAL 7- 37
To properly control termination of a bus cycle for a bus error or retry condition, TA and
TEA must be asserted and negated for the same rising edge of BCLK. Table 7-5 lists the
control signal combinations and the resulting bus cycle terminations. Bus error and retry
terminations during burst cycles operate as described in 7.4.2 Line Read Transfers and
7.4.4 Line Write Transfers.
Table 7-5. and Assertion Results
Case No. Result
1High Low Bus Error—Terminate and Take Bus Error Exception,
Possibly Deferred
2Low Low Retry Operation—Terminate and Retry
3 Low High Normal Cycle Terminate and Continue
4 High High Insert Wait States
7.6.1 Bus Errors
The system hardware can use the TEA signal to abort the current bus cycle when a fault
is detected. A bus error is recognized during a bus cycle when TA is negated and TEA is
asserted. When the processor recognizes a bus error condition for an access, the access
is terminated immediately. A line access that has TEA asserted for one of the four long-
word transfers aborts without completing the remaining transfers, regardless of whether
the line transfer uses a burst or burst-inhibited access.
When TEA is asserted to terminate a bus cycle, the M68040 can enter access error
exception processing immediately following the bus cycle, or it can defer processing the
exception. The instruction prefetch mechanism requests instruction words from the
instruction memory unit before it is ready to execute them. If a bus error occurs on an
instruction fetch, the processor does not take the exception until it attempts to use the
instruction. Should an intervening instruction cause a branch or should a task switch
occur, the access error exception for the unused access does not occur. Similarly, if a bus
error is detected on the second, third, or fourth long-word transfer for a line read access,
an access error exception is taken only if the execution unit is specifically requesting that
long word. Otherwise, the line is not placed in the cache, and the processor repeats the
line access when another access references the line. If a misaligned operand spans two
long words in a line, a bus error on either the first or second transfer for the line causes
exception processing to begin immediately. A bus error termination for any write accesses
or for read accesses that reference data specifically requested by the execution unit
causes the processor to begin exception processing immediately. Refer to Section 8
Exception Processing for details of access error exception processing.
When a bus error terminates an access, the contents of the corresponding cache can be
affected in different ways, depending on the type of access. For a cache line read to
replace a valid instruction or data cache line, the cache line being filled is invalidated
before the bus cycle begins and remains invalid if the replacement line access is
terminated with a bus error. If a dirty data cache line is being replaced and a bus error
occurs during the replacement line read, the dirty line is restored from an internal push
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