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7- 36 M68040 USER’S MANUAL MOTOROLA
C1 C2
A31–A0
BCLK
BYTE
SIZ1
TT1, TT0
TM2–TM0
D31–D0
UPA1, UPA0
CIOUT
TS
TIP
TA
R/W
SIZ0
BREAKPOINT
ACKNOWLEDGE
C1 C2
WRITE STACK
Figure 7-25. Breakpoint Interrupt Acknowledge Bus Cycle Timing
7.6 BUS EXCEPTION CONTROL CYCLES
The M68040 bus architecture requires assertion of TA from an external device to signal
that a bus cycle is complete. TA is not asserted in the following cases:
The external device does not respond.
No interrupt vector is provided.
Various other application-dependent errors occur.
External circuitry can provide TEA when no device responds by asserting TA within an
appropriate period of time after the processor begins the bus cycle. This allows the cycle
to terminate and the processor to enter exception processing for the error condition. TEA
can also be asserted in combination with TA to cause a retry of a bus cycle in error.
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