Loading...
xviii M68040 USER’S MANUAL MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
4-5 Instruction-Cache Line State Diagram ......................................................... 4-14
4-6 Data-Cache Line State Diagram .................................................................. 4-16
5-1 Functional Signal Groups ............................................................................. 5-4
6-1 M68040 Test Logic Block Diagram .............................................................. 6-2
6-2 Bypass Register ........................................................................................... 6-6
6-3 Output Latch Cell (O.Latch) ......................................................................... 6-7
6-4 Input Pin Cell (I.Pin) ..................................................................................... 6-7
6-5 Output Control Cells (IO.Ctl) ........................................................................ 6-8
6-6 General Arrangement of Bidirectional Pins .................................................. 6-8
6-7 Circuit Disabling IEEE Standard 1149.1A .................................................... 6-14
6-8 Clock Input Timing Diagram ......................................................................... 6-22
6-9 TRST Timing Diagram .................................................................................. 6-22
6-10 Boundary Scan Timing Diagram .................................................................. 6-23
6-11 Test Access Port Timing Diagram ............................................................... 6-23
7-1 Signal Relationships to Clocks..................................................................... 7-2
7-2 Internal Operand Representation ................................................................. 7-3
7-3 Data Multiplexing ......................................................................................... 7-4
7-4 Byte Enable Signal Generation and PAL Equation ...................................... 7-5
7-5 Example of a Misaligned Long-Word Transfer............................................. 7-7
7-6 Example of a Misaligned Word Transfer ...................................................... 7-7
7-7 Misaligned Long-Word Read Transfer Timing ............................................. 7-8
7-8 Byte, Word, and Long-Word Read Transfer Flowchart ................................ 7-10
7-9 Byte, Word, and Long-Word Read Transfer Timing..................................... 7-11
7-10 Line Read Transfer Flowchart...................................................................... 7-14
7-11 Line Read Transfer Timing .......................................................................... 7-15
7-12 Burst-Inhibited Line Read Transfer Flowchart ............................................. 7-18
7-13 Burst-Inhibited Line Read Transfer Timing .................................................. 7-19
7-14 Byte, Word, and Long-Word Write Transfer Flowchart ................................ 7-20
7-15 Long-Word Write Transfer Timing ................................................................ 7-21
7-16 Line Write Transfer Flowchart ...................................................................... 7-23
7-17 Line Write Transfer Timing........................................................................... 7-24
7-18 Locked Transfer for TAS Instruction Timing ................................................ 7-27
7-19 Interrupt Pending Procedure ........................................................................ 7-30
7-20 Assertion of IPEND ...................................................................................... 7-30
7-21 Interrupt Acknowledge Bus Cycle Flowchart ............................................... 7-32
7-22 Interrupt Acknowledge Bus Cycle Timing .................................................... 7-33
7-23 Autovector Interrupt Acknowledge Bus Cycle Timing .................................. 7-34
7-24 Breakpoint Interrupt Acknowledge Bus Cycle Flowchart ............................. 7-35
7-25 Breakpoint Interrupt Acknowledge Bus Cycle Timing .................................. 7-36
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com