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7- 32 M68040 USER’S MANUAL MOTOROLA
The interrupt acknowledge bus cycle is a read transfer. It differs from a normal read cycle
in the following respects:
1. TT1 and TT0 = $3 to indicate an acknowledged bus cycle.
2. Address signals A31–A0 are set to all ones ($FFFFFFFF).
3. TM2–TM0 are set to the interrupt request level (the inverted values of IPL2–IPL0).
The responding device places the vector number on the data bus during the interrupt
acknowledge bus cycle, and the cycle is terminated normally with TA. Figures 7-21 and
7-22 illustrate a flowchart and functional timing diagram for an interrupt acknowledge cycle
terminated with TA .
ACKNOWLEDGE INTERRUPT
1) LATCH VECTOR NUMBER
ACQUIRE DATA
START NEXT CYCLE
3) DRIVE A31–A0 TO $FFFFFFFF
4) DRIVE UPA1, UPA0 TO $0
5) SET SIZE TO BYTE
6) SET TRANSFER TYPE ON TT1, TT0 TO $3
7) PLACE INTERRUPT LEVEL ON TM2–TM0
PROCESSOR EXTERNAL DEVICE
PROVIDE VECTOR INFORMATION
TERMINATE CYCLE
1) PLACE VECTOR NUMBER ON BYTE D7–D0
2) ASSERT TRANSFER ACKNOWLEDGE (TA)
1) REMOVE DATA FROM D7–D0
2) NEGATE TA
REQUEST INTERRUPT
8) NEGATE CIOUT
9) ASSERT TS FOR ONE CLOCK
10) ASSERT TIP
1) IPEND RECOGNIZED, WAIT FOR 
INSTRUCTION BOUNDARY
2) SET R/W TO READ
Figure 7-21. Interrupt Acknowledge Bus Cycle Flowchart
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