Loading...
7- 28 M68040 USER’S MANUAL MOTOROLA
Clock 2 (C2)
During the first half of the first clock cycle after C1, the processor negates TS. The
selected device uses R/W, SIZ1, SIZ0, A1, and A0 to place its information on the data
bus. With the exception of R/W, these signals also select any or all of the bytes (D24–
D31, D16–D23, D15–D8, and D7–D0). Concurrently, the selected device asserts TA. At
the end of the first clock cycle after C1, the processor samples the level of TA and
latches the current value on the data bus. If TA is asserted, the read transfer terminates,
and the latched data is passed to the appropriate memory unit. If TA is not recognized
asserted, the processor ignores the data and appends a wait state instead of
terminating the transfer. The processor continues to sample TA on successive rising
edges of BCLK until TA is recognized as asserted. The latched data is then passed to
the appropriate memory unit. If more than one read cycle is required to read in the
operand(s), C1 and C2 are repeated accordingly.
When the processor recognizes TA at the end of the last read transfer for the locked
bus cycle, it negates TIP during the first half of the next clock.
Clock Idle (CI)
The processor does not assert any new control signals during the idle clock states, but it
may begin the modify portion of the cycle at this time. The R/W signal remains in the
read mode until C3 to prevent bus conflicts with the preceding read portion of the cycle;
the data bus is not driven until C4.
Clock 3 (C3)
During the first half of C3, the processor places valid values on the address bus and
transfer attributes and drives R/W low for a write cycle. The processor asserts TS to
indicate the beginning of a bus cycle. The TIP signal is also asserted at this time to
indicate that a bus cycle is active.
LOCKE is asserted during C3 for the last write transfer of the locked sequence. If
multiple write transfers are required for misaligned operands or multiple operands,
LOCKE is asserted only for the final write transfer. The external arbiter can use this
indication to distinguish between two back-to-back locked bus cycles and allow
arbitration between them.
Clock 4 (C4)
During the first half of C4, the processor negates TS and drives the appropriate bytes of
the data bus with the data to be written. All other bytes are driven with undefined values.
The selected device uses R/W, SIZ1, SIZ0, A1, and A0 to latch the information on the
data bus. Any or all of the bytes (D31–D24, D23–D16, D15–D8, and D7–D0) are
selected by SIZ1, SIZ0, A1, and A0. Concurrently, the selected device asserts TA. At
the end of C4, the processor samples the level of TA ; if TA is asserted, the bus cycle
terminates. If TA is not recognized asserted at the end of C4, the processor appends a
wait state instead of terminating the transfer. The processor continues to sample the TA
signal on successive rising edges of BCLK until it is recognized asserted.
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com