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MOTOROLA M68040 USER’S MANUAL 7- 25
MC68LC040 memory units and Appendix B MC68EC040 for information on the
MC68EC040 memory unit.
The processor asserts TS during C1 to indicate the beginning of a bus cycle. If not
already asserted from a previous bus cycle, the TIP signal is also asserted at this time
to indicate that a bus cycle is active.
Clock 2 (C2)
During the first half of the first clock after C1, the processor negates TS and drives the
data bus with the data to be written. The selected device uses R/W, SIZ1, and SIZ0 to
latch the data on the data bus. Concurrently, the selected device asserts TA and either
negates or asserts TBI to indicate it can or cannot support a burst transfer. At the end of
the first clock after C1, the processor samples the level of TA and TBI. If TA is asserted,
the transfer terminates. If TA is not recognized asserted, the processor inserts wait
states instead of terminating the transfer. The processor continues to sample TA and
TBI on successive rising edges of BCLK until TA is recognized asserted.
If TBI was negated with TA , the processor continues the cycle with C3. Otherwise, if TBI
was asserted, the line transfer is burst inhibited, and the processor writes the remaining
three long words using long-word write bus cycles. Only in this case does the processor
increment A3 and A2 for each write, and the new address is placed on the address bus
for each bus cycle. Refer to 7.4.3 Byte, Word, and Long-Word Write Transfers for
information on long-word writes. If no waits states are generated, a burst-inhibited line
write completes in eight clocks instead of the five required for a burst write.
Clock 3 (C3)
The processor drives the second long word of data on the data bus and holds the
address and transfer attribute signals constant during C3. The selected device
increments A3 and A2 to reference the next long word, latches this data from the data
bus, and asserts TA. At the end of C3, the processor samples the level of TA ; if TA is
asserted, the transfer terminates. If TA is not recognized asserted at the end of C3, the
processor inserts wait states instead of terminating the transfer. The processor
continues to sample TA on successive rising edges of BCLK until TA is recognized
asserted.
Clock 4 (C4)
This clock is identical to C3 except that the value driven on the data bus corresponds to
the third long word of data for the burst.
Clock 5 (C5)
This clock is identical to C3 except that the value driven on the data bus corresponds to
the fourth long word of data for the burst. After the processor recognizes the last TA
assertion and terminates the line write bus cycle, TIP remains asserted if the processor
is ready to begin another bus cycle. Otherwise, the processor negates TIP during the
first half of the next clock. The processor also three-states the data bus during the first
half of the next clock following termination of the write cycle.
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