Clock 2 (C2)
During the first half of the clock after C1, the processor negates TS and drives the
appropriate bytes of the data bus with the data to be written. All other bytes are driven
with undefined values. The selected device uses R/W, SIZ1, SIZ0, A1, A0, and CIOUT
to latch only the required information on the data bus. With the exception of R/W and
CIOUT, these signals also select any or all of the bytes (D31–D24, D23–D16, D15–D8,
and D7–D0). If the first clock after C1 is not a wait state, then the selected peripheral
device asserts the TA signal.
At the end of the first clock cycle after C1, the processor samples the level of TA,
terminating the bus cycle if TA is asserted. If TA is not recognized asserted at the end of
the clock cycle, the processor ignores the data and inserts a wait state instead of
terminating the transfer. The processor continues to sample TA on successive rising
edges of BCLK until TA is recognized asserted. The data bus then three-states and the
bus cycle ends.
When the processor recognizes TA at the clock edge and terminates the bus cycle, TIP
remains asserted if the processor is ready to begin another bus cycle. Otherwise, the
processor negates TIP during the first half of the next clock. The processor also three-
states the data bus during the first half of the next clock following termination of the
write transfer.
7.4.4 Line Write Transfers
The processor uses line write bus cycles to access a 16-byte operand for a MOVE16
instruction and to support cache line pushes. Both burst and burst-inhibited transfers are
supported. Figures 7-16 and 7-17 illustrate a flowchart and functional timing diagram for a
line write bus cycle.
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