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MOTOROLA M68040 USER’S MANUAL 7- 17
Clock 5 (C5)
This clock is identical to C3 except that once TA is recognized, the latched value
corresponds to the third long word of data for the burst. After the processor recognizes
the last TA assertion and terminates the line read bus cycle, TIP remains asserted if the
processor is ready to begin another bus cycle. Otherwise, the processor negates TIP
during the first half of the next clock.
Figures 7-12 and 7-13 illustrate a flowchart and functional timing diagram for a burst-
inhibited line read bus cycle.
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